1. Field of the Invention
The present invention relates to a defect detection method, and more particularly, to a method of detecting defects on the backside of a semiconductor sample.
2. Description of the Prior Art
In the semiconductor fabricating process, some small particles and defects are unavoidable. As the size of devices shrinks and the integration of circuits increases gradually, those small particles or defects have an even greater effect on the properties of the integrated circuits. In order to improve the reliability of semiconductor devices, a plurality of tests and failure analyses are performed continuously to find the root cause of the defects or particles. Then, process parameters can be tuned correspondingly to reduce a presence of defects or particles so as to improve the yield and reliability of the semiconductor fabricating process.
Please refer to FIG. 1. FIG. 1 is a schematic diagram of a method of defect detection 10 according to the prior art. As shown in FIG. 1, a sampling 12 is first performed to select a semiconductor wafer as a sample for following defect detection and analysis in advance. Next, a defect inspection 14 is performed. Normally, a proper defect inspection machine is utilized to scan in a large scale to detect all defects on the semiconductor wafer. Since there are too many defects on a semiconductor wafer, a manual defect review with the SEM cannot be directly performed for all defects in practice. Hence, a manual defect classification 16 is typically performed before the defect review 18. After separating the defects into different defect types, some defects are sampled for the defect review 18. Next, a defect root cause analysis 20 may be performed in advance according to the result of the defect review 18 to attempt to reduce the defect generation.
In the prior art technology, the biggest problem lies in the determination of defects from the samples. Typically, there may be thousands of defects found in the defect inspection 14. However, engineers are only able to pick a portion of the defects, such as 50 to 100, to perform the defect review 18 and the following defect analysis. In general, the determination of the killer defects, which often have a large impact on the yield of fabrication processes, is totally dependent upon the personal experience of the engineers and most of the time, the engineers are only able to randomly pick up some samples for the defect review 18. Thus, in most cases, since the samples in the defect review 18 are picked up randomly, it is obvious that only a few effective samples are valid and most parts of the defect review 18 are meaningless and ultimately, this leads to a huge waste of time and effort, and a great reduction in the accuracy of the following defect analysis.
In addition to most defects that are located on the surface of the semiconductor wafer, which can be analyzed by a front side approach to perform a failure analysis, some defects strongly related to fabrication processes are located on the bottom layer or backside of the wafer and normally, defects that are hidden within the wafer are the most difficult to detect, especially for chips with multi-layer metal wires. Hence, a backside approach referred to as the layout navigation system has been recently introduced to perform a much more accurate failure analysis for determining the location of the defect. Nevertheless, circuit layout diagrams needed for the layout navigation system are highly confidential materials for most companies and are difficult to obtain. Consequently, the difficulty of obtaining the circuit layout diagrams often increases fabrication time and cost, and influences the reliability, electrical performance, yield, and overall production when the fabs are performing defect analysis. Therefore, there has been a strong demand for developing a defect detection method for solving the above-mentioned problems.